Dataflow Computing for AI Inference with Kunle Olukotun - #751
Episode
57 min
Read time
2 min
Topics
Productivity, Remote Work, Startups
AI-Generated Summary
Key Takeaways
- ✓Dataflow vs Instructions: Reconfigurable dataflow architectures configure hardware to match PyTorch computation graphs rather than fetching instructions each cycle, using token-based synchronization instead of locks and barriers, achieving 2-3x higher HBM bandwidth utilization than GPUs through asynchronous parallel execution.
- ✓Decoder Fusion Strategy: Mapping an entire LLama decoder across 16 RDU chips in space eliminates intermediate data movement across HBM boundaries, creating a fused kernel that provides flash attention benefits across the whole decoder rather than just attention mechanisms, dramatically reducing memory bandwidth requirements.
- ✓Multi-Model Serving: The SN40L chip includes 1.5TB DDR memory alongside 64GB HBM, enabling 5 trillion total parameters resident simultaneously with millisecond model switching latency, allowing high utilization while serving custom fine-tuned models without dedicating separate accelerators per model.
- ✓Dynamic Architecture Evolution: Research focuses on dynamic reconfigurable dataflow using streaming tensor programs to handle mixture-of-experts models, variable context lengths, and sparse computations by enabling runtime graph reconfiguration at sub-microsecond latency rather than static microsecond-scale mapping used in current generation systems.
What It Covers
Kunle Olukotun explains how SambaNova's reconfigurable dataflow architecture achieves 5-10x better performance per watt for AI inference by eliminating instruction fetching, maximizing memory bandwidth utilization, and enabling microsecond model switching across trillion-parameter systems.
Key Questions Answered
- •Dataflow vs Instructions: Reconfigurable dataflow architectures configure hardware to match PyTorch computation graphs rather than fetching instructions each cycle, using token-based synchronization instead of locks and barriers, achieving 2-3x higher HBM bandwidth utilization than GPUs through asynchronous parallel execution.
- •Decoder Fusion Strategy: Mapping an entire LLama decoder across 16 RDU chips in space eliminates intermediate data movement across HBM boundaries, creating a fused kernel that provides flash attention benefits across the whole decoder rather than just attention mechanisms, dramatically reducing memory bandwidth requirements.
- •Multi-Model Serving: The SN40L chip includes 1.5TB DDR memory alongside 64GB HBM, enabling 5 trillion total parameters resident simultaneously with millisecond model switching latency, allowing high utilization while serving custom fine-tuned models without dedicating separate accelerators per model.
- •Dynamic Architecture Evolution: Research focuses on dynamic reconfigurable dataflow using streaming tensor programs to handle mixture-of-experts models, variable context lengths, and sparse computations by enabling runtime graph reconfiguration at sub-microsecond latency rather than static microsecond-scale mapping used in current generation systems.
Notable Moment
Olukotun reveals SambaNova maintains 5x lower latency than GPUs even at high batch sizes because tensor parallelism with overlapped communication remains efficient on dataflow architectures, while GPUs cannot effectively hide communication latency, fundamentally changing the throughput-latency tradeoff curve.
Episode Transcript
We have a data flow problem, right? So let's build a data flow computer, right? So let's build a computer that matches the data flows as represented by the algorithm in the hardware. So why does it need to be reconfigurable? Well, because you don't have one graph. Right? You it's your it's the it's how you change what the what the hardware does. You reconfigure it. Alright, everyone. Welcome to another episode of the Twindler AI podcast. I am your host, Sam Charrington. Today, I'm joined by Kunle Olukotun. Kunle is a professor of electrical engineering and computer science at Stanford University and cofounder and chief technologist at SambaNova Systems. Before we get going, be sure to take a moment to hit that subscribe button wherever you're listening to today's show. Kunle, welcome back to the podcast. It has been a minute. Good to be back and, glad to be here. We were just chatting. It was, I think at a, when we first spoke back in 2018. Clearly a very different world in AI since then, and it is going to be really good to catch up with you and, what's been new in your research and at SambaNova. Let's get started by having you share a little bit about your background and what you've been working on recently. Well, thank you for having me on again, and it's, good to be back on on the, the the cast podcast. And, you know, my background is is, you know, is computer architect, well known, for doing some of the, pioneering multicore work, back in the in the mid nineties, and, done a lot of work on parallel programming environments using domain specific languages. And, this work has has led to to the, work we're doing now in research and, at San Benova about how to take, reconfigurable data flow architectures and, efficiently execute, these domain specific language models, to create environments that are better for doing AI computation. Right? And so, our focus is on how you, do very efficient fast inference on big models, as energy efficiently as possible. Right? And so, the focus has been on on very large models, you know, models with, trillions of parameters that can fit in a single rack, on models that, are good for agentic solutions, where you've got hundreds of agents that, potentially, need to, work together and and switch between these agents with very low latency, and then sort of very fast inference because you, have interactive environments that you want to support, multiple LM model calls, sequentially for a chain of thought, kinds of, reasoning or because you've got a workflow that requires lots of all end calls. Yeah. You mentioned in there the idea of reconfigurable data flow architecture. Let's kinda step back for a second and talk a little bit about, you know, what that means. What is a a reconfigurable data flow architecture, and where does that idea come from? Well, it comes basically …
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