The Professor of Outputmaxxing — Anjney Midha, AMP

What It Covers

Anjney Midha, CEO of AMP, explains how his company operates as an independent system operator for compute — modeled on electric grid utilities like PJM Interconnect — pooling 1.3 gigawatts of supply across clouds and silicon to eliminate stranded capacity and serve frontier AI labs.

Key Questions Answered

• •GPU Cluster Utilization Benchmarks: Node utilization below 96% in AI clusters is indefensible — Google treated anything under 95% as an outage. MFU (model flop utilization) best-in-class sits at 60–70%. Most singleton clusters fall short of both metrics due to misalignment between capital providers and the engineers actually managing infrastructure at scale.
• •Community-Aligned Data Center Pricing: Up to 20% of US data centers face community backlash risk in the current year. A concrete mitigation: charge $4.50 per compute-hour instead of $4.00, routing the $0.50 margin directly to local communities as cash or electricity bill reductions. This converts opposition into partnership without requiring regulatory intervention.
• •Independent System Operator Model for Compute: Rather than owning assets, AMP pools demand from frontier labs and supply from trusted 20-plus-year data center operators at 1.3 gigawatt base load, targeting 6 gigawatts over four years. Labs receive guaranteed base load with flexible spike capacity — mirroring how PJM Interconnect coordinates uncorrelated industrial demand across the Northeast US grid.
• •Culture as a Fragile Daily Practice, Not a Moat: Anthropic's coding dominance traces directly to four years of resource scarcity forcing precise prioritization — coding as the singular P-zero toward AGI. Teams flush with capital skip this definition process. Culture requires daily action-based reinforcement; without hardship forcing trade-off clarity, lab cultures become brittle before reaching capability takeoff.
• •Trust Boundary as the Primary Chip Company Risk: Hardware startups like Matx adopt NVIDIA's open reference architecture to eliminate data center integration battles, focusing innovation on systems co-design at the logic tile level. The real bottleneck is trust access — chip tape-out cycles run two years, so without early visibility into next-generation model architectures, chips arrive mismatched to production workloads.