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Chips, Memory, and Power | Pat Gelsinger

54 min episode · 2 min read
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Pat Gelsinger

Episode

54 min

Read time

2 min

Topics

Relationships, Startups, Fundraising & VC

AI-Generated Summary

Key Takeaways

  • ✓Chip Design vs. Manufacturing Gap: AI tools can compress chip design to three months, but silicon fabrication, advanced packaging, and rack-scale integration still require nine months minimum before deployment. This mismatch means workload assumptions made at design time are often obsolete by the time chips reach production scale, as demonstrated by Graphcore's trajectory.
  • ✓Memory Innovation Threshold: Zero major new memory architectures — beyond DRAM, SRAM, and Flash — have emerged in thirty years, largely because memory was a loss-making industry four out of every five years. The AI workload's memory-intensive nature has added roughly $2.5 trillion in memory sector market cap over four years, finally creating capital conditions for breakthrough materials like ferroelectrics.
  • ✓Energy as Economic Ceiling: US national energy capacity grew at approximately 4% annually after a decade of near-zero net growth, as coal retirements offset renewable additions. Because energy capacity directly equals economic capacity in an AI-driven economy, data center projects will increasingly default when promised power cannot be delivered — Oracle's situation signals the first of many such failures.
  • ✓AI Chip Consolidation Incoming: The current proliferation of roughly 100 specialized AI inference accelerator chips will consolidate for three reasons: workload requirements shift faster than specialized silicon can adapt, capital markets will concentrate around winning architectures, and dominant players like OpenAI and Anthropic will select preferred hardware partners, effectively standardizing around a small number of platforms.
  • ✓Optical Networking Transition Timeline: Copper interconnects become more expensive than optical at distances beyond approximately five meters, making the 2028–2029 timeframe the projected inflection point for co-packaged optics adoption in scale-up GPU clusters. NVL72's manufacturing complexity demonstrated that a mature optical supply chain would have accelerated AI cluster deployment by roughly 18 months.

What It Covers

Playground Global General Partner Pat Gelsinger joins a16z's Raghu Raghuram and Guido Appenzeller to map the next bottlenecks in AI infrastructure — chip manufacturing timelines, memory bandwidth limitations, power capacity constraints, optical networking transitions, and how virtualization principles apply to agent-based computing systems.

Key Questions Answered

  • •Chip Design vs. Manufacturing Gap: AI tools can compress chip design to three months, but silicon fabrication, advanced packaging, and rack-scale integration still require nine months minimum before deployment. This mismatch means workload assumptions made at design time are often obsolete by the time chips reach production scale, as demonstrated by Graphcore's trajectory.
  • •Memory Innovation Threshold: Zero major new memory architectures — beyond DRAM, SRAM, and Flash — have emerged in thirty years, largely because memory was a loss-making industry four out of every five years. The AI workload's memory-intensive nature has added roughly $2.5 trillion in memory sector market cap over four years, finally creating capital conditions for breakthrough materials like ferroelectrics.
  • •Energy as Economic Ceiling: US national energy capacity grew at approximately 4% annually after a decade of near-zero net growth, as coal retirements offset renewable additions. Because energy capacity directly equals economic capacity in an AI-driven economy, data center projects will increasingly default when promised power cannot be delivered — Oracle's situation signals the first of many such failures.
  • •AI Chip Consolidation Incoming: The current proliferation of roughly 100 specialized AI inference accelerator chips will consolidate for three reasons: workload requirements shift faster than specialized silicon can adapt, capital markets will concentrate around winning architectures, and dominant players like OpenAI and Anthropic will select preferred hardware partners, effectively standardizing around a small number of platforms.
  • •Optical Networking Transition Timeline: Copper interconnects become more expensive than optical at distances beyond approximately five meters, making the 2028–2029 timeframe the projected inflection point for co-packaged optics adoption in scale-up GPU clusters. NVL72's manufacturing complexity demonstrated that a mature optical supply chain would have accelerated AI cluster deployment by roughly 18 months.

Notable Moment

Gelsinger revealed he first declared copper interconnects obsolete approximately 25 years ago — a prediction still unrealized today. He acknowledged the irony directly, noting that physics and economics are finally aligning to make optical the default for all input-output functions, just decades later than originally anticipated.

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Episode Transcript

In a AI digital age, energy capacity equals economic capacity. Why build a new data center and buy the million GPUs if I can't power that? You're gonna see more and more defaults happening on many of those data center projects because the energy won't be there. Whenever you have the technology to make something easy, that means the bottleneck moves somewhere else. Nothing's a chip anymore. It's a rack. It took me three months to design it, but it's nine months until I can actually start to use it. Exactly how many major new memories have you had over the last thirty years? Zero. Memory innovation for the first time in thirty years is nigh upon us. I declared the death of copper about twenty five years ago. Eventually, I'll be right for all of us hardware guys. This is like Renaissance in front of AI inference accelerator chips, and I'm sure I don't even know them all. Why are you guys funding so many of those anyway? You've funded your fair share of truth. Thank you. Historically, there have not been a 100 competing processor vendors in any industry ever. Is this a temporary thing? It'll convert back to a view? I see it as AI is making it faster to design chips, but actually building them, powering them, and connecting them may be getting harder. In this episode, a 16 z's Raghuraguram and Guido Abenzeler sit down with Pat Gelsinger, general partner at Playground Global and former CEO of Intel and VMware to discuss the next bottlenecks in AI infrastructure. Pat takes us back to his early days designing Intel's processors when engineers were inventing the tools they needed to build the chips themselves. He explains why AI could bring a similar shift today even as manufacturing timelines, memory bandwidth, and power become harder constraints. They also debate whether the explosion of specialized AI chips will last, why Pat believes memory innovation is finally approaching a breakthrough, and how optical networking could change the architecture of AI clusters. In drawing on their shared history at VMware, they close with a question. What would it look like to rebuild virtualization for a world where AI agents, rather than humans, are the primary users? I'm here with our esteemed guest and dear friend and former boss, mister Pat Gessinger. Welcome, Pat. Pat is currently the general partner at Playground Global, but as you are very, very well known in the industry for leading Intel, for being the CTO of Intel, of course, leading VMware and many other things. So welcome. Hey. Thank you, Raghu. Great to be with you and Guido. Great. And to me, this feels just a little bit like old home. Right? We superimposed a year of change. Right? But you both look the same. I feel energetic. So let's dive in. There has never been a day when you stopped being energetic, so there's no news there. But, yeah, no. Let's start actually from your …

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