What will computer chips look like in 2045?

What It Covers

Dwarkesh Podcast explores semiconductor manufacturing with Intel leadership, covering how chips advance from research labs to high-volume production, why AI demand has outpaced capacity by 40-50%, how transistor architectures evolve over decades, and why equipment bottlenecks at suppliers like ASML constrain the entire industry's ability to scale through 2030.

Key Questions Answered

• •Innovation pacing in chip nodes: Intel learned from its 10nm delay (originally targeted 2016, shipped 2018) that cramming too much innovation into one node breaks schedules. The current discipline involves phase-gate maturity metrics with defined yield, defect, and performance criteria that a technology must hit before advancing. Limiting innovation per node keeps customer delivery timelines predictable, which matters more than maximizing technical ambition in any single generation.
• •Transistor architecture roadmap: Chip transistors evolved from planar (1960) to FinFET (volume production 2011) to Gate All Around (Samsung, 2022), with each step wrapping the gate around more sides of the channel to prevent current leakage as transistors shrank. CFET, which stacks n-type and p-type transistors vertically rather than side-by-side, is the next architecture under research and could theoretically double transistor density per area, though heat dissipation remains a fundamental constraint.
• •Backside power delivery as a differentiator: Intel's decision to route power lines beneath the wafer rather than above the transistors frees up front-side wiring space, reducing pitch requirements enough that a single High NA EUV pass suffices. TSMC, lacking backside power, still requires double patterning with High NA, making the $400M+ machines uneconomical for them. Architecture choices at the process level directly determine which lithography tools deliver return on investment.
• •Copper-to-ruthenium interconnect crossover: Copper wiring requires a resistive liner layer for adhesion. As wire pitches shrink below roughly 20 nanometers, that liner consumes a disproportionate share of the conduction path. Ruthenium can be etched directly without a liner, giving it lower effective resistivity at those dimensions. Intel is actively researching ruthenium as a replacement for the tightest interconnect layers, while copper remains optimal for wider lines.
• •Equipment supply as the hard ceiling on AI compute scaling: ASML produces fewer than 100 EUV machines annually with no plans to significantly exceed that by decade's end. This output is shared across Intel, TSMC, Samsung, and memory makers. Intel's CTO estimates the industry could realistically achieve roughly 2x leading-edge wafer output, not the 10x that AI's historical 3x annual compute growth would require. Orders placed today face 18-month tool lead times, pushing meaningful new capacity to 2028 at earliest.
• •Hybrid bonding as the packaging scaling path: Hybrid bonding eliminates solder bumps by directly fusing copper interconnects between chips under heat and pressure, enabling connection pitches that have dropped from 130-150 micrometers historically to under 10 micrometers today in Intel's labs. Published research already demonstrates reliability at 0.45 micrometer pitch, another order-of-magnitude improvement. At sub-micron pitches, packaging connections approach the density of on-chip wiring layers, enabling power reduction measured in picojoules per bit for chip-to-chip interfaces.